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stv0502 ccd sensors analog processor ic october 1998 . serial bus control video . correlated double sampling of the ccd signal . digitally controlled variable ampli- fier and black clamp level . 8 bits pixel rate adc audio . microphone preamp with switchable agc (range 34db - 60db) or fixed gain description the chip integrates the analog functions needed in a ccd video camera, more particularly for video- conferencing purpose. the ccd signal is sampled, amplified to a useful level and digitized by an 8 bits adc. the gain of the amplifier and the black level clamp can be adjusted by a serial bus. the audio microphone preamplifier allows a micro- phone to be connected to the chip, which outputs a differential audio line level signal ready for digital conversion or straight amplification. the preampli- fier incorporates an agc to adapt to the income signal level. the agc is switchable on/off by the serial interface. tqfp44 full (10 x 10 x 1.40mm) (plastic quad flat pack) order code : stv0502 33 32 31 30 29 1 2 3 4 5 40 41 42 43 44 18 19 20 21 22 data6 data5 data4 af_out- af_out+ v cc cagc v cc gnd sdata_io v ss ob fcds fs 8 9 10 11 7 6 16 17 14 15 12 13 28 27 26 25 24 23 39 38 37 36 35 34 sclk adc_clock gnd micro_in mic_ref acc v bias v dd data0 data1 data2 data3 v dd data7 not used not used v ss vagcin cds_out cds_ref cds_in gnd v cc v top v bot black_ref not used ob_cap agc level test only 0502-01.eps pin connections 1/15
pinout description pin signal ana./dig. type description 1 vagcin analog i video variable gain input 2 cds_out analog o cds output 3 cds_ref analog - cds reference 4 cds_in analog i cds input 5v ss digital - adc data ground 8 data[7] digital o adc output - msb 9 data[6] digital o adc output 10 data[5] digital o adc output 11 data[4] digital o adc output 12 data[3] digital o adc output 13 data[2] digital o adc output 14 data[1] digital o adc output 15 data[0] digital o adc output - lsb 16 v dd digital - adc data supply 17 v dd digital - digital supply 18 sdata_io digital i/o serial interface data wire 19 v ss digital - digital ground 20 ob digital i ob pulse 21 fcds digital i fcds pulse 22 fs digital i fs pulse 23 sclk digital i serial bus clock wire 24 adc_clock digital i adc clock input pulse 25 gnd analog - microphone ground 26 micro_in analog - microphone input 27 micro-ref analog - microphone internal reference 28 acc analog - microphone preamplifier dc level capacitor 29 cagc analog - microphone preamplifier agc capacitor 30 af_out+ analog o microphone preamplifier output (diff. +) 31 af_out- analog o microphone preamplifier output (diff. -) 32 v cc analog - microphone preamplifier supply 33 v bias analog - microphone internal supply (regulated) 34 v cc analog - adc supply 35 gnd analog - adc ground 36 vtop analog - adc top reference 37 vbot analog - adc bottom reference 38 test only analog - test only (agcout/adcin) 39 agclevel analog - audio agc threshold configuring pin 40 ob_cap analog - black clamp dc loop capacitor 42 black_ref analog - video voltage reference 43 v cc analog - video supply 44 gnd analog - video ground 6-7 41 nc nc - - - - not to be connected not to be connected 0502-01.tbl stv0502 2/15
v ref bias vreg psrr g = 1 g = 1 g = 1 correlated double sampling g = 1 bias agc audio interface 6db/18db range 0-18db a/d conv comp d/a conv serial bus interface video gain amplifier & a/d converter interface black level adjust & clamp stv0502 0502-02.eps block diagram functional description 1 - video section a ccd signal is provided to the stv0502, via a coupling capacitor, as well as the pulses fs/fcds. the cds (correlated double sampling) is perform- ing a clamp of the ccd signal during the fcds pulse. the signal obtained is then sampled during the fs pulse, and held the rest of the period. the resulting signal is then the difference between the useful pixel level, and the pixel level corresponding to no charge which can vary from one pixel to another. therefore, the parasitic level offset from one pixel to another is removed. this signal is dc coupled to the acg, amplified by a variable gain amplifier, bus controlled (0.07db step), which gain is in the range +6db to +23.7db (17.7db range). typically, the amplifier is controlled in order to keep the signal at an optimum level (agc) to be digitized. an extra 12db can be added up via a bit of the serial interface. in this case the gain range becomes +18db up to + 36db. at this point, the signal is clamped to a black level during the ob pulse. the black level is 5 bits bus controlled, and its range corresponds to [0 lsb ; 31 lsb] of the adc. the black level is made with a 5 bits dc frequency dac, using the same v bottom and v top voltage references than the adc for matching purposes. the clamp is made out of a ob pulse sampled comparator between the dac output voltage (black) and the adc input signal. the comparator has a symetrical current output charging a capacitor. the obtained voltage is buffered and used as a feedback to the agc input stage. this clamp makes sure that adcin is matched to the dac black setting during the ob pulse, disregarding any offset in the agc path. then the signal is digitized by a fast adc, clocked at the pixel rate. the output of the chip is then an 8-bit pixel data, ready for digital post-processing. 2 - audio section the chip integrates a high gain audio amplifier, in order to process low signals coming from a speech microphone, and provide on its output a line level, differential audio signal, for digital conversion, or power amplification. two modes can be selected : fixed gain mode or agc mode. in case of agc mode, a peak detection of the signal is performed in order to regulate the output signal on a defined level of 1.5v pp or 1v pp (non-diff). this regulated level can be chosen at 1.5v pp or 1v pp thanks to a pin at respectively ground or supply voltage (a pull- up resistor to supply is already included on chip), for compatibility purposes between the 502 and various back-end chips. the system includes a low-noise fixed amplifier (26db), and a bias circuitry at the front. stv0502 3/15
cds_in fcds t1 t2 t4 t3 t prop t dadc pixel n 3 clk pipe-line delay fs cds_out adc_in adc_clock data_out sampling period pixel n+1 pixel n+2 pixel n+3 pixel n+4 pixel n+5 pixel n-4 pixel n-3 pixel n-2 pixel n-1 pixel n pixel n+1 pixel n pixel n+1 pixel n+2 pixel n+3 pixel n+4 0502-03.eps notation : - t1 is the delay between the falling edge of fcds and the beginning of the active pixel level from the ccd. - t2 is the delay between the falling edge of fs and the end of the active pixel level from the ccd. t1, t2, t3 and t4 must be kept > 0 in the application. -t prop is the propagation delay between cds_out and adc_in signals (within the agc block). -t dadc is the delay on the adc outputs between the rising edge of the clock and data output. figure 1 functional description (continued) it is followed by a voltage controlled amplifier (range 8db - 34db), that can be switched into a fixed 26db gain amplifier. the vca output is differential and 2 buffers are driving the two output pins, with a load impedance down to 5k w . a bias circuitry and an external capacitor (acc) form a dc feedback loop on the vca dc bias, in order to correct any dc offset on the vca output. finally, a peak detector (double alternance) is used to compare the output signal with the reference threshold, to be regulated at. an external capacitor (cagc) is used for the agc time constants. if the signal goes above the threshold, a 500 m a current is charging the capacitor with a fast reponse time(attack). in case of very big signals, a second charge cureent of about 5ma is given, in order to reduce the period during which the output signal is saturated. otherwise, a constant 1 m a current dis- charges the capacitor with a slow response time (decay). the capacitor voltage controls the vca gain. this constitues the agc loop. fs cds_out fcds cds_in = ccd signal feedtrough level signal level 0502-04.eps figure 2 stv0502 4/15
functional description (continued) 3 - serial bus specification it is a 2-wires (data and clock) serial bus, used as a slave. clock line is monodirectional (input) and allways sent by the master to the chip, whereas data line is bidirectional (i/o). there are 3 registers (8 bits), both writable/readable. each register can be addressed by a 4 bits address word, followed by a r/w bit, and an 8 bits word data (read/write). 2 main patterns can be sent : reset pattern and read/write pattern. 3.1 -timings and protocol the data bit is taken into account when the clock is rising. - reset pattern : resets all the registers to their default (power on) values : format = 16 * (data=1) | 2 * (data=0) (total = 18 clocks) - read/write pattern : format = 4 addr bits | r/w bit | 8 data bits (total = 13 clocks) please note that : 1/ on power on conditions, sdata line is in write (input) mode. 2/ in case of a read pattern, the sdata line is automatically set to read (output mode) during 8 clock cycles (data d7 - d0) after r/w bit has been sent, and comes back in write (input mode) after the 13th clock cycle. 3/ there is no timing restriction between two consecutive patterns (a pattern being defined as one of the two above). 3.2 - register summary register address (a3-a0) data format (d7-d0) video amplifier gain 0000 dddd.dddd black level adjust 0001 xxxd.dddd video high gain select 0001 xxdx.xxxx test mode 0001 ddxx.xxxx microphone agc 0010 xxxx.xxxd x : unused bits d : means useful bits please note that 3 different functions are merged in register address 01. clk sdata reset pattern 1 2 3 4 5 6 7 8 9 10111213141516 1 2 2 clk cycles minimum 16 clk cycles 0502-05.eps figure 3 clk sdata read/write pattern a3 a2 a1 a0 r/w d7 d6 d5 d4 d3 d2 d1 d0 12345678910111213 0502-06.eps figure 4 stv0502 5/15
functional description (continued) 3.3 - control data video amplifier gain control (8 bits used) address : 0000 por value : 0000.0000 ---> 6db gain is expressed from cdsoutput to adc input (adc range 1.55v pp ) - 0.07db / lsb step - overall range (256 steps) : 17.7db video gain (db) data 6 0000.0000 6.07 0000.0001 6.14 0000.0010 ... ... 7.12 0001.0000 7.19 0001.0001 ... ... 23.63 1111.1110 23.7 1111.1111 black level adjustment control (5 bits used) address : 0001 por value : 0001.0000 ---> 16lsb the adjustment is controlling the black reference voltage. however, it is preferred to express the black level adjustment in terms of the adc output code variation (in adc lsbs, compared to the nominal default setting) depending on the black setting. typically, 16 lsbs black level is recommended. - 1 adc lsbs / lsb step - overall range : 31 adc lsbs black level (adc ouput variation) data 0 lsbs xxx0.0000 1 lsbs xxx0.0001 ... ... 30 lsbs xxx1.1110 31 lsbs xxx1.1111 video high gain select (1 bit used) address : 0001 por value : 0 ---> nominal gain this bit controls an extra 12db gain in the video path (adding to gain described in previous page). video high gain select data nominal gain xx0x.xxxx extra 12db gain xx1x.xxxx video agcout test signal on/off (2 bits used) address : 0001 por value : 00 ---> high z pad a pin is reserved to output the adc input signal, or input the adc input signal for test and evaluation purpose. those bits control the state of the output buffer. to limit xtalk and pollutions, the buffer is in high impedance mode during normal operation. vagcout pin state data normal operation (high z pin) 00xx.xxxx agc output test 10xx.xxxx adc input test 11xx.xxxx microphone agc switch (1 bit used) address : 0010 por value : 0000.0000 ---> agc off the switch is controlling the state of the agc : on or off. in off mode, the micro preamp. is set at a fixed nominal gain of 52db. in on mode, the agc is operating in a gain range [34db ; 60db] (see further in this document for details). microphone agc data off 0000.0000 on 0000.0001 stv0502 6/15
thermal data symbol parameter value unit r th (j-a) junction-ambient thermal resistance max. 65 o c/w 0502-03.tbl electrical characteristics t amb = 25 o c, v dd = v cc = 5v, unless otherwise specified symbol parameter test conditions min. typ. max. unit supply v cc , v dd all supplies 4.5 5 5.5 v i sup total current consumption v cc = v dd = 5v 40 55 70 ma cmos digital inputs v il v ih low level input voltage high level input voltage 0.7 v dd 0.3 v dd v v i il i ih low level input current high level input current -1.0 1.0 m a m a cmos digital outputs (4ma drivers) v ol v oh low level output voltage high level output voltage 2.4 0.4 v v i ol i oh low level output current high level output current 4.0 -4.0 ma ma serial interface slevel sdata, sclk levels cmos v f clk bus clock frequency 0.5 1 mhz dutyc clock duty cycle sclk 40 50 60 % t dr delay between clk rising edge and data out read mode, see figure 5 300 500 700 ns t dw delay between clk rising edge and data in write mode, see figure 5 300 500 700 ns t r clock rise time sclk 200 ns t f clock fall time sclk 200 ns 0502-04.tbl sdata_io t r t f t dr t dw sclk 0502-07.eps figure 5 absolute maximum ratings symbol parameter value unit v dd , v cc supply voltage -0.5, 7 v v i digital input pin voltage -0.5, v dd + 0.5 v i i digital input pin current 1.6 ma t stg storage temperature +80 o c t oper operating temperature 0, +70 o c t lead lead temperature (10s max.) +260 o c esd : the stv0502 withstands 2kv in human body model and 100v in machine model for all pins versus v dd and v ss . 0502-02.tbl stv0502 7/15
electrical characteristics t amb = 25 o c, v dd = v cc = 5v, unless otherwise specified (continued) symbol parameter test conditions min. typ. max. unit video cds r in input resistance pin 4 8 11 14 k w c in input capacitance pin 4 6 pf indyn input dynamic range pin 4, before output clipping 0.6 0.7 v pp cds_sr s/h slew rate pin 2, fs high 0.6 0.9 v/15ns cds_dr s/h droop rate pin 2, fs low -20 +20 mv/ m s cds_hm s/h hold mode feed through pin 2, fs low, f in = 1mhz -55 -45 db cds_lin cds linearity pin 2, 500mv pp (1) 0.3 1.5 % cds gain overall input to output gain pin 2, normal operation -2 -1 0 db r out cds output impedance pin 2, fcds & fs high 250 w outload cds ouput load 100 w fs ps pulse width see timings 12 ns fcds fsds pulse width see timings 12 ns pix_fre pixel rate pins 4, 21, 22 6 12 mhz psrr power supply rejection measured on pin 2 (2) 60 db video amplifier r in input resistance pin 1 2 k w c in input capacitance serial bus from h00 to hff 18 pf min. gain max. gain minimum gain maximum gain serial bus = h00/no extra gain serial bus = hff/no extra gain 23.2 6 23.7 6.5 db db min. gain max. gain minimum gain maximum gain serial bus = h00/extra gain serial bus = hff/extra gain 35.2 12 35.7 12.5 db db gset-err gain setting relative error serial bus from h00 to hff -0.5 0.5 db out_max max. output signal before clipping pin 38, v cc = 4.5v g = 6db, v in = 0.8v pp g = 23.7db, v in = 0.1v pp 1.6 1.6 v pp v pp t r output rise time square input 10 15 ns t f output fall time square input 10 15 ns t prop agc propagation time pin 1 to pin 38 15 20 ns psrr power supply rejection measured on pin 38 (2) 45 db xtalk xtalk from video to audio measured on pin 38, compared to pins 20 and 21 (2) 60 db notes : 1. normal operation means fs & fcds run at specified timings and 12mhz frequency. 2. on a 20hz to 10mhz frequency range, with 10 m f filtering capacitors on all supplies, and well splitted supplies and grounds. 0502-05.tbl stv0502 8/15
electrical characteristics t amb = 25 o c, v dd = v cc = 5v, unless otherwise specified (continued) symbol parameter test conditions min. typ. max. unit 8 bits adc & ob clamp ob_rise ob high time constant pin 38, ob 0 to 1 4 mv/ m s ob_decay ob low time constant pin 38, ob 1 to 0 -2 mv/ms blk_ran black level adjust range pins 8 to 15, ob high, serial bus from h00 to h1f 31 lsbs blk_res black level adjust resolution pins 8 to 15, per serial bus lsb step 1 lsbs blk_lev black level adjust pins 8 to 15 bus = h00 bus = h1f 29 0 31 2 33 lsbs lsbs adc_dn adc input dynamic range (output from 0 to 255) pin 38 test signal above black clamping level (v bot ) 1.4 1.55 1.7 v pp f clk adc clock frequency pin 24 12 mhz t pclk output pipeline delay (3) from a sampling to data out 3 3 clk cycles t dadc clock to data out (4) clk positive edge, c load = 20pf 17 ns r ladd ladder resistance between pins 36 and 37 330 w v top top reference voltage pin 36 3.2 3.35 3.5 v v bot bottom reference voltage pin 37 1.71 1.8 1.89 v adc_lin adc linearity data out, input signal between [v bot + 25mv ; v top - 25mv] 1% notes : 3. the signal is being sampled as long as adc_clk is high. 4. see figure 6 for data reading timing constraint. 0502-06.tbl sampling period pixel n data available on falling edge of clock t dadc pixel n-4 pixel n-3 pixel n-2 pixel n-1 pixel n adc_in adc_clock data_out pixel n+1 0502-08.eps figure 6 due to t dadc , and to make sure the data are read when they are stable, please read the data on the falling edge of the adc clock. stv0502 9/15
electrical characteristics t amb = 25 o c, v dd = v cc = 5v, unless otherwise specified (continued) symbol parameter test conditions min. typ. max. unit microphone preamplifier v bias bias audio voltage pin 26 3.8 v in_ref micro input voltage pin 33 2 v r in input impedance pin 33 50 k w g fix overall gain agc mode off 48 50 52 db g agc overall gain agc mode on v agc = 0.5v v agc = 4v 54 56 20 58 34 db db alc1 alc2 regulated output level on pins 30/31, agc on, input = [1.5mv pp ; 30mv pp ] agclevel (pin 39) = 0 agclevel (pin 39) = 5 1.1 0.7 1.5 1 1.9 1.3 v pp v pp ich agc charge current on pin 29 when signal out above threshold 500 m a idis agc discharge current all the time with agc on -1 m a t att output response time step +6db, c agc = 2.2 m f5ms t dec output response time step -6db, c agc = 2.2 m f 2.5 s out_max output clipping level pins 30/31 agc off : v in = 5mv pp agc on : v in > 40mv pp 1.7 1.7 2 2 v pp v pp out_dc output dc voltage pins 30/31 2.1 v out_of channel dc mismatch pins 30/31 -350 0 350 mv r out output impedance pins 30/31 100 w thd overall thd 1v pp out, 1khz signal, bw 15khz 0.15 0.4 % psrr psrr from v cc f = 1khz, v cc + sine 100mv pp (2) 60 db cmrr cmrr from v cc f = 1khz, v cc + sine 100mv pp (2) 60 db lfc low cut-off frequency c in = 2.2 m f, c acc = 10 m f 250 hz hfc high cut-off frequency c in = 2.2 m f, c acc = 10 m f 20 khz xtalk xtalk from video to audio measure on pins 30/31, compared to pin 38 (2) 60 db notes : 2. on a 20hz to 10mhz frequency range, with 10 m f filtering capacitors on all supplies, and well splitted supplies and grounds. 0502-07.tbl input output +6db -6db t dec t att 0502-09.eps figure 7 stv0502 10/15
i/o diagrams 1 vagcin 8.67k w 1.33k w 0502-10.eps figure 8 : vagcin 3 cds_ref 0502-12.eps figure 10 : cds_ref 2 cds_out 0502-11.eps figure 9 : cds_out 4 cds_in 10k w 0502-13.eps figure 11 : cds_in data[7:0] pins 8 to 15 0502-14.eps figure 12 : data[7:0] sdata_io 220 w 18 0502-15.eps figure 13 : sdata_io ob, fcds, fs sclk, adc_clock pins 20, 21, 22, 23, 24 220 w 0502-16.eps figure 14 : ob, fcds, fs, sclk, adc_clock 26 micro_in 0502-17.eps figure 15 : micro_in stv0502 11/15
i/o diagrams (continued) 27 mic_ref 0502-18.eps figure 16 : mic_ref cagc 29 0502-20.eps figure 18 : cagc acc 28 0502-19.eps figure 17 : acc af_out+, af_out- pins 30/31 10k w 10k w 0502-21.eps figure 19 : af_out+, af_out- 33 v bias 22k w 0502-22.eps figure 20 : v bias 36 v top 10k w 330 w 0502-23.eps figure 21 : v top 37 v bot 330 w 10k w 40k w 0502-24.eps figure 22 : v bot 38 vagcout 0502-25.eps figure 23 : vagcout stv0502 12/15
i/o diagrams (continued) 39 agclevel 0502-26.eps figure 24 : agclevel 42 black_ref 0502-28.eps figure 26 : black_ref 40 ob_cap 0502-27.eps figure 25 : ob_cap stv0502 13/15
sclk serial interface sdata adc_clock microphone 2.2 m f 6.8 m f line outputs ob fcds fs 10 m f v dd adc 10 m f 1 m f 10 m f from ccd 33nf v dd data[7] data[6] data[5] data[4] data[3] data[2] data[1] data[0] 1 m f v cc video 1 2 3 4 5 6 7 8 9 10 16 17 18 19 20 26 27 28 29 30 36 37 38 40 11 12 13 14 15 21 22 23 24 31 32 33 34 35 25 39 41 42 43 44 cds_out cds_in vagcin data[7] data[6] data[5] data[4] data[3] data[2] v dd v dd sdata_io ob fcds fs sclk adc_clock v cc micro_in acc cagc af_out+ af_out- v cc v cc v top v bot ob_cap testonly black_ref agclevel nc cds_ref gnd nc nc gnd ob data[1] data[0] v bias micro_ref gnd gnd gnd 10 m f v cc micro 1 m f 1 m f 220nf stv0502 10 m f 3.3k w 5.1k w 1k w 3 x 1n4148 10 m f 0502-29.eps typical application stv0502 14/15
44 34 d3 e 12 22 1 11 c b a1 a2 a d1 d 23 33 e3 e1 e l k l1 0,25 mm .010 inch gage plane 0,10 mm .004 inch seating plane pm-4y.eps package mechanical data 44 pins - full plastic quad flat pack (thin) (tqfp) dimensions millimeters inches min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.40 0.012 0.015 0.016 c 0.09 0.20 0.004 0.008 d 12.00 0.472 d1 10.00 0.394 d3 8.00 0.315 e 0.80 0.031 e 12.00 0.472 e1 10.00 0.394 e3 8.00 0.315 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 k0 o (min.), 7 o (max.) 4y.tbl information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no licence is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or s ystems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 1998 stmicroelectronics - all rights reserved purchase of i 2 c components of stmicroelectronics, conveys a license under the philips i 2 c patent. rights to use these components in a i 2 c system, is granted provided that the system conforms to the i 2 c standard specifications as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the neth erlands singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com stv0502 15/15

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